1. Field of the Invention
The present invention relates generally to memory devices and more particularly to a nonvolatile memory device having a page read operation.
2. Description of Related Art
Nonvolatile memory devices typically include a memory array comprising memory cells that maintain their data even when electrical power has been removed from the device. There are a variety of types of nonvolatile memory devices. One type includes so-called “read only memory,” like mask ROM in which the data is stored in the memory cell by implanting impurities in the channel region of MOS transistors. The data stored in mask ROM devices, and other nonvolatile read only memory devices, cannot be changed in the field. Another type of nonvolatile memory device includes electrically erasable and programmable memory cells, such as flash memory. The data stored in flash memory cells, and other nonvolatile electrically erasable and programmable memory cells, can be changed in the field using electronic programming and erasing procedures. Representative flash memory technologies include floating gate memory cells and charge trapping memory cells such as SONOS, NROM, PHINES and the like.
There are a variety of biasing procedures that are used for programming and erasing memory cells in flash memory. The biasing procedures for floating gate memory cells and charge trapping memory cells cause tunneling of electrons and/or holes into and out of the floating gates or charge trapping structures. The concentration of charge held in the floating gates or the charge trapping structures has an effect on the threshold voltage of the memory cell. Thus, by controlling the amount of charge held in the floating gates or in the charge trapping structures, the threshold voltage of the memory cell can be set, and data stored.
Because of variations in memory cell characteristics, variations in voltages applied, and variations in other parameters across an array, the biasing procedures used for programming and erasing operations in flash memory can result in nonuniform levels of charge stored in the cells distributed across the array. Therefore, the biasing procedures applied in many devices include a sequence of programming or erasing pulses with verify operations between each pulse, or between each set of pulses. A typical verify process includes driving word line voltages to program verify or erasing verify levels, which are changed slightly from the standard read level in order to provide program or erase margin. Then, data is sensed one byte or one word at a time from the memory cells to determine whether each cell has been successfully programmed or erased. If the verify process fails, then retry program or erase pulses are applied iteratively until a successful verify is achieved, or a maximum number of retries is reached.
For many types of flash memory, the erase process is executed on relatively large sectors of memory cells at a time. In some devices, the erase process includes a pre-program operation over the entire sector, followed by an erase operation over the entire sector, and then followed by a so-called soft program process over the entire sector. In some cases, verify operations are also executed after soft program processes. Background information showing erase and program operations with verify can be found in U.S. Pat. Nos. 6,496,417 and 5,912,845. The verify operations for these types of devices require that all of the words in the sector be verified in sequence. This verify operation is quite time-consuming, and contributes a large proportion of time to the overall erase timing for the device.
Due to demand for faster access times combined with large, high-density arrays for flash memory, page read and burst read flash memories have been developed. In normal flash memory, the read operation is executed word by word so that within a specified time, such as time after address transition (TAA of for example 100 ns to 70 ns or less) or time after a chip enable signal (TCE), only one 16-bit word is addressed, its contents sensed, and its data output. In page mode devices, the output structure for the array is set up to provide for addressing more than one word at a time, such as four words (64 bits) or more, within the TAA or TCE time. The multi-word page of data is sensed in parallel out of the array, and stored in sense amplifiers or in page buffers. Data stored in the sense amplifiers or page buffers can be read out in burst mode or otherwise with very short cycle times, that are not directly limited by the TAA or TCE times of the flash memory array.
To further improve speed of operation of flash memory devices, page mode flash devices have been developed which support page programming in addition to page reading. To program a page in the array, a page buffer is loaded with data to be programmed, by transferring data into bit latches in the page buffer, and programming the page with each bit line being controlled by the data in the corresponding bit latch. A verify procedure for page mode programming can include automatically clearing bit latches in the page buffer which are successfully programmed, in a parallel operation. The data stored in the page buffer is then read byte-by-byte to confirm that all bits have been cleared to indicate a successful page program operation. See for example, U.S. Pat. No. 5,835,414 by Hung; and U.S. Pat. No. 5,638,326 by Hollmer. In the just cited patent by Hung, the data is sensed and stored in the page buffer and then judged (by comparison to an all ones or all zeros pattern) in parallel using a match circuit that produces a signal (ALBRES1) indicating when all bit latches in the page buffer have been reset. This process can reduce the speed of the verify operations significantly, by eliminating the requirement that each byte stored in the page mode sense amplifiers, or in bit latches of the page buffer, be read one by one for the judgment step in the verify procedure.
However, as the size of memory arrays increases, the likelihood of defects in the array increases. To address the likelihood of defects, redundancy techniques have been developed. According to typical redundancy techniques, a redundant array is included on the integrated circuit device, including a redundant set of sense amplifiers. When a defective cell is found in the main array, a replacement cell from the redundant array is used in its place. Addressing signals and output paths are rerouted to access the replacement cell automatically during operation of the device. See, U.S. Pat. No. 6,065,090 by Deas and U.S. Pat. No. 6,643,794 by Utsugi for background information. The new routing for replacement cells creates difficulties for page mode verify operations. In particular, where the verify operation is coupled with the page mode sense amplifiers or page buffers in the array, accurate results cannot be obtained without rerouting results from a replacement cell into the page mode sense amplifiers or page buffers. Such rerouting could alter the timing characteristics for the sensing operation by several nanoseconds, or amounts that are not acceptable for high-performance devices. Another alternative-would require the verify operation for page mode devices to be executed word by word after the data has been repaired and selected for output using an output multiplexer. The replacement cell output can be mapped into the output multiplexer more easily, without seriously affecting timing of the sensing operation. However, the judgment step in the verify operation in this case fails to take advantage of page mode operation, slowing down the overall program and erase timing characteristics for the device.
It is desirable therefore to provide a page mode memory architecture which supports redundancy and high-speed verify operations in support of program and erase procedures.